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| AutoESL’s AutoPilot High-Level Synthesis Tool Achieves BDTI Certification |
By BDTI, 2/16/2010
 BDTI recently completed an in-depth analysis of AutoESL’s AutoPilot high-level synthesis tool via the BDTI High-Level Synthesis Tool Certification Program™. BDTI evaluated the process of implementing applications on a Xilinx FPGA using AutoPilot, comparing it with traditional FPGA design based on hand-written RTL code, and with DSP processor software development. Overall, AutoPilot demonstrated a strong ability to generate high-quality RTL code—with equivalent resource utilization to hand-written RTL code.
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| Texas Instruments Introduces New Multi-Core System-on-Chip Architecture |
By BDTI, 2/16/2010
 TI has unveiled a new chip-level architecture for high-performance, multi-core DSP-processor-based SoCs. Most notable among its features are new on-chip and chip-to-chip interconnection mechanisms, an upgraded high-performance DSP core, and both hardware and tools support for programming concurrent applications. The architecture is optimized to run at 1.0 to 1.2 GHz in 40 nm process technology.
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| Jeff Bier's Impulse Response: Compilers Can Erase Architectural Advantages |
By Jeff Bier, 2/16/2010
Back in the early 1990’s, compilers for DSP processors were pretty lame. Even if a compiler generated code that was functionally correct (which, sadly, wasn’t always the case) the code was usually far from efficient. At the time, this wasn’t a big deal: DSP applications were still fairly small (in terms of lines of code), and DSP processor architectures weren’t nearly as complex as they are today. A reasonably skilled DSP software engineer could optimize an application by hand, sometimes entirely in assembly language, without using a compiler at all.
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| Case Study: Developing Attention-Getting Demos |
By BDTI, 2/16/2010
Your company just developed the most powerful chip ever. Your job: to get customers interested in using it in their system designs. Challenging? You bet. As fantastic as its capabilities may be, your little slab of black plastic looks pretty much just like those of your competitors. Yes, the numbers on your brochure look great. But, let’s face it, they’re just numbers on paper. How exciting can they be?
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| BDTI Unveils High-Level Synthesis Tools Certification Program Results |
By BDTI, 1/20/2010
 This week BDTI released the first results from its High-Level Synthesis Tools Certification Program (HLSTCP). The first tools to achieve certification are AutoESL’s AutoPilot and Synfora’s PICO. Additional certifications will be released on an ongoing basis, as agreements with tool vendors allow. The HLSTCP helps engineers and managers understand the capabilities of high-level synthesis (HLS) tools and assess when to consider these tools for their designs. HLS tool vendors can use the program to validate and improve the quality of results and productivity provided by their tools. (HLS tools are also referred to as electronic system level [ESL] synthesis, C synthesis, behavioral synthesis, or algorithmic synthesis tools.)
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| New ADI Blackfin Integrates Large Executable Flash for Control Applications |
By BDTI, 1/20/2010
 Analog Devices, Inc. (ADI) has announced new members of the Blackfin processor family targeting control-loop applications. The new BF50x parts sport a much larger “executable” flash in place of the serial flash offered in earlier Blackfin chips, and integrate a 12-bit analog-to-digital converter suitable for control applications.
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| Jeff Bier’s Impulse Response—Small Processor Companies Have it Tough—But Not Impossible |
By Jeff Bier, 1/20/2010
It’s a tough world out there for small processor companies. It’s tough to attract new customers, and tough to support the ones you manage to get. A key challenge is the trend towards customers consolidating their purchasing: many system companies prefer to use fewer unique processors in their systems, for both business and technical reasons. From a business standpoint, using fewer different processors (and thus, using fewer vendors) can help streamline procurement and provide negotiating leverage with suppliers. And from a technical standpoint, using fewer different processors can simplify development and facilitate re-use of software and know-how.
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| Case Study: Technical Due Diligence |
By BDTI, 1/20/2010
Although the economy appears to be on the mend, established technology companies and venture capitalists alike remain cautious about their investments. When considering investments, acquisitions or major product purchase decisions, they are wary of accepting companies’ claims about their technology at face value and often turn to outside experts for technical due diligence evaluations to assess and manage risk.
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| MIPS Launches MicroMIPS Architecture with Two New Cores |
By BDTI, 12/16/2009
 This month MIPS introduced two new cores, the M14K and M14Kc, that are based on a new instruction set architecture called microMIPS. MicroMIPS uses a mixed-width 16/32-bit instruction set to improve code density relative to the MIPS32 instruction set architecture. In general, processors with smaller program memory requirements require less on-chip and off-chip memory, and less memory bandwidth. This can translate into reduced cost and power consumption. Since cost and power are key metrics for many embedded applications, 16-bit compressed instruction sets have become fairly common.
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| CEVA Simplifies DSP Software Development |
By BDTI, 12/16/2009
 This month CEVA announced significant improvements to its software tool suite. Collectively, the new tools and features are dubbed the CEVA Application Optimizer, and are part of the CEVA-Toolbox software development suite. CEVA describes these capabilities as providing an “end-to-end, fully C-based development flow.” This is an important topic for users of DSP processors, who are less and less willing to write heavily target-specific C code or assembly code which requires them to become architecture experts.
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